Currently, a display part of a multimedia device may be generally divided into two parts: a main control chip and a display module group. The main control chip includes a processor, a graphics engine module, a video codec module, and a display control module, and is configured to send obtained image data to the display module group by using a specific interface protocol according to a user requirement. The display module group includes a display screen and a display driving chip, and is mainly configured to receive, according to a particular interface protocol, image data sent by the main control chip and convert the image data into a scanning signal of the screen.
With development of microelectronic technologies, the main control chip of a multimedia device has developed from an ASIC (Application Specific Integrated Circuit: application specific integrated circuit) to an SOC (System On Chip) chip based on an AXI (Advanced eXtensible Interface: advanced extensible interface) bus. Generally, the SOC chip has a display control module, which is configured to read a processed image (such as an image decoded by a decoding module or drawn by a graphics processing unit) from a DDR (Double Data Rate: double data rate synchronous dynamic random access memory) and send the image to the display module group.
Using an SOC chip as the main control chip effectively reduces the volume of a product and shortens the development period of the product, but at the same time, brings a certain limitation. An AXI bus is added in the display control module; therefore, latency (Latency) increases for the display control module to read a burst (burst) of data from the DDR. This latency varies according to different system loads and bus frequency states, so that the real-timeness of such a real-time (real time) service module as the display control module cannot be guaranteed.
To resolve the real-timeness issue, an existing SOC technology generally resolves the latency by raising a priority of the display control module in the AXI bus, adding a buffer (Buffer), and increasing a frequency and a data bit width of the AXI bus. The following are two common methods:
Method 1: Reduce the latency by adding a buffer. In a diagram of architecture of a main control chip shown in FIG. 1, a main control chip 109 includes a display control module 107, advanced extensible interface buses 101 and 102, and DDR controllers 103 and 104, where the display control module 107 connects to a display module 108. Two DDRCs 103 and 104 (DDR Controller: DDR controller), which connect to the advanced extensible interface AXI buses 101 and 102 of the man control chip, connect to DDRs 105 and 106, respectively. One of the two DDRCs 103 and 104 is set especially for a display buffer and certain multimedia applications, and bus architecture and display architecture are optimized accordingly to guarantee the real-timeness requirement of display.
Defects of the structure are as follows:
1. By using double DDRs and corresponding design, the area of the chip increases as the display buffer increases. This raises a design cost and at the same time increases system power consumption. For a multimedia play field, especially a mobile multimedia field such as a mobile phone, the power consumption issue is not acceptable.
2. Since the display architecture and bus architecture are adjusted and optimized accordingly, an underlying driver needs to be re-developed so that the underlying driver supports an open operating system. This brings a high product cost.
Method 2: Set a high priority for the display control module in the AXI bus of the SOC main control chip to preferentially guarantee bandwidth, increase the frequency and data bit width of the bus to provide absolute bandwidth supply, and raise the display buffer to guarantee display bandwidth, thereby ensuring that a splash screen or erratic display does not occur.
This method has the following defects:
1. After a high priority is configured for the display control module in the AXI bus, the display control module occupies most high-priority bandwidth in the AXI bus. This lowers utilization efficiency of DDR bandwidth. To improve bandwidth utilization efficiency of the DDR bandwidth, a system needs to operate at a relatively high frequency. This inevitably raises the operating power consumption of the system.
2. While a high priority is configured for the display control module in the AXI bus, the real-timeness of other real-time service modules is surely affected during the running process of the display control module. This increases their latency, thereby affecting the overall efficiency of the system.